IBM Unveils Groundbreaking Sub-1 Nanometer Chip Technology
WHO:
Techmeme - IBM, industry leaders, Huiming Bu (VP of IBM Semiconductors Global R&D), Jay Gambetta (Director of IBM Research)
WHAT:
Fast Company - IBM unveiled what it calls a “major semiconductor breakthrough” with the introduction of the world’s first sub-1 nanometer chip technology.
Fast Company - The new chip technology is projected to offer up to 50% more performance or 70% greater energy efficiency than IBM’s 2 nm node chips.
Fast Company - IBM claims a 40% improvement in SRAM, which is important in AI inference.
Ars Technica - IBM's nanostack transistors could boost chip performance or energy efficiency.
Fast Company - The new chip “node” can pack 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm node chip.
Fast Company - The new chip architecture incorporates three sheets each 5 nanometers thick, with a distance between sheets of 9 nanometers.
Fast Company - Huiming Bu stated, “We have entered a domain in semiconductor manufacturing [that] works between magic and physics.”
Fast Company - IBM will announce manufacturing partners for the sub-nanometer chips “at a later time,” according to Jay Gambetta.
Techmeme - IBM claims its new chip technology can maintain chip innovation for 10 years.
Fast Company - The new chip architecture introduces a "nanostack" design, which builds on the nanosheet architecture used in the 2 nm chip process.
Fast Company - IBM's new chip architecture can be customized for CPUs, GPUs, and mobile chips.
Techmeme - IBM unveiled a 0.7nm chip manufacturing process utilizing a "nanostack" 3D transistor architecture.
Fast Company - The new chip technology can pack 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm node chip.
Fast Company - The new chip is projected to offer up to 50% more performance or 70% greater energy efficiency than IBM’s 2 nm node chips.
Fast Company - IBM claims a 40% improvement in SRAM, which is important in AI inference.
WHERE:
Fast Company - IBM is partnering with Japanese foundry Rapidus to scale manufacturing of 2 nm process chips.
WHEN:
Fast Company - IBM aims to deploy sub-nanometer chip technology commercially in the next five years.
WHY:
Fast Company - Achieving sub-nanometer scale is a key industry milestone for smaller, more powerful, and more energy-efficient chips.
HOW:
Fast Company - The sub-nanometer chips feature stacks of transistors staggered across two separate wafers, connected by an innovative dielectric bond.
Fast Company - The manufacturing process involves depositing each layer atom by atom.
Fast Company - The sub-nanometer chips feature stacks of transistors staggered across two separate wafers, connected by an innovative dielectric bond.
Fast Company - The sub-nanometer chips utilize an innovative dielectric bond connecting staggered stacks of transistors across two separate wafers.
Fast Company - The manufacturing process involves depositing each layer atom by atom.
(UPDATED June 25, 2026 17:40 UTC)
IBM has announced a significant semiconductor breakthrough with the introduction of the world’s first sub-1 nanometer chip technology, which is expected to deliver up to 50% more performance and 70% greater energy efficiency compared to its 2 nanometer node chips. The new chips feature stacks of transistors arranged across two separate wafers, connected by a cutting-edge dielectric bond, and the manufacturing process involves depositing each layer atom by atom. Additionally, IBM claims a 40% improvement in SRAM, which plays a crucial role in AI inference.
--
(UPDATED June 25, 2026 15:53 UTC)
IBM has unveiled a groundbreaking advancement in chip technology with its new nanostack transistors, which have the potential to significantly enhance chip performance and energy efficiency. This innovative chip architecture can fit an astonishing 100 billion transistors onto a chip the size of a fingernail, nearly doubling the density of IBM's previous 2 nanometer node chip, and features three sheets each just 5 nanometers thick, spaced 9 nanometers apart. According to Huiming Bu, we are now operating in a realm of semiconductor manufacturing that straddles the line between magic and physics, and IBM plans to announce its manufacturing partners for these sub-nanometer chips at a later time.
--
(UPDATED June 25, 2026 13:40 UTC)
IBM has announced that its new chip technology is set to sustain innovation for the next decade. This cutting-edge architecture introduces a "nanostack" design that builds on the existing nanosheet framework used in the 2 nanometer chip process, and it can be tailored for various applications, including CPUs, GPUs, and mobile chips. The sub-nanometer chips utilize stacks of transistors arranged across two distinct wafers, linked by a groundbreaking dielectric bond.
--
(UPDATED June 25, 2026 11:53 UTC)
IBM has unveiled a groundbreaking 0.7 nanometer chip manufacturing process that employs a "nanostack" 3D transistor architecture, allowing for an impressive 100 billion transistors on a chip the size of a fingernail. This new technology is projected to deliver up to 50% more performance and 70% greater energy efficiency compared to IBM's existing 2 nanometer chips, with a notable 40% improvement in SRAM, which is crucial for AI inference. To scale manufacturing, IBM is partnering with Japanese foundry Rapidus and aims to deploy this sub-nanometer chip technology commercially within the next five years.